Most conventional Very Large Scale Integrated (VLSI) systems are built according to the so-called “System-on-Chip” (SoC) concept.
SoC functionalities are the result of cooperation between several simpler modules which are generally selected by designers from a pre-existing library. The designers' role is to map the SoC functions onto that of the modules of the library. However, effective communication and interconnection systems are needed in order to meet suitable performances for the designed SoC system, and in particular, to provide an effective communication between the modules of the system.
As system complexity increases, on-chip communication becomes more and more critical. Conventional on-chip communication systems are complex infrastructures aimed at providing suitable performances. In addition, in the next few years, SoCs will include hundreds of communicating blocks running at many GHz. Such systems are known as multiprocessor System-on-Chips (MP-SoCs).
In conventional pre-deep submicron technology, the delay in VLSI systems is mainly due to logic cells. Due to technology improvements, gate delay tends to decrease while wires provided between the communicating modules have more and more impact on the overall delay involved during a communication. Accordingly, in conventional MP-SoCs, on-chip communication will limit the performance of such systems.
One of the main limitations relating to clock frequency is due to synchronization, which is supposed to guarantee that all communicating blocks meet the timing requirements and correctly exchanges data. Conventional synchronization techniques are getting more difficult due to wire delay problems and to increases in design complexity. In particular, timing requirements often lead to heavy constraints on interconnection wires and clock tree wires used to provide the communicating modules with clock signals. Accordingly, with the increasing wire delay problems and complexity, huge design efforts often require coping with synchronization issues, reducing productivity and increasing time-to-market.
Conventional design efforts fail to cope with clock distribution problems, wire delay balancing and, in general, to cope with synchronization.
Researchers have recently proposed the so-called Network-on-Chip (NoC) concept to overcome the limitations relating to the huge efforts necessary to adequately design on-chip communication systems. NoC aims at providing scalable and flexible communication architectures with suitable performance, even for future MP-SoCs. Moreover, NoCs provide the SoC architects with a tool for designing on-chip communication systems quickly, thus increasing productivity and reducing time-on-market.
NoC, however, is not a centralized architecture and is intended to be physically implemented as a distributed communication infrastructure. NoCs are nevertheless based on a packed-switched communication concept and are mainly composed of three NoC modules, namely: a router, a Network Interface (NI) and a link. However, the synchronization issues impose a heavy scalability limitation also for NoC architectures and solutions at the architectural level and must be provided to fully enable the NoC deployment.
Conventional clock distribution strategies have been already proposed to cope with synchronization issues. In particular, some techniques have been proposed to perform synchronization for synchronizing modules in an integrated circuit in which the module clocks have the same frequency but are potentially out of phase with an arbitrary constant phase difference.
Exploiting clock periodicity, periodic synchronizers predict whether incoming data switch in correspondence to arising clock edge or not. If periodic synchronizers detect a potential conflict between data switching and the clock at the receiving side, they delay either the rising edge or the data to avoid metastability.
In particular, in integrated circuits in which the communicating modules are clocked using clock signals having the same frequency but being out of phase with a constant arbitrary phase difference, which are usually called “mesochronous” systems, the periodic synchronizer can adjust the clock or data phase once for all the modules. Being done once, the synchronization phase can last an arbitrary amount of time, such that it is even possible to wait for metastability to decay.
Two main classes of periodic synchronizers have therefore been developed, namely delay line synchronizers and two register synchronizers. Delay line synchronizers use a variable delay placed on data lines. The delay on data is calculated to avoid switching in the metastability window of receiving registers. However, this solution is expensive, due to the presence of a variable delay line in each data path.
Two registers synchronizers insert a delay on the clock signal rather than on the data signal. Two registers are clocked by a direct clock and a delayed clock, respectively. The output of the register driven by the proper clock is chosen by means of a conflict detector which is able to detect the phase relationship between data and clock. It can be implemented in several ways, but generally comprises phase detectors, forbidden zone detectors and failure detectors such that it generally has a very complicated and extensive structure.
There is therefore a need for synchronization techniques to synchronize modules in an integrated circuit. There is also a need for techniques to synchronize communication blocks in VLSI circuits.